The present invention relates generally to memory devices and, more particularly, to a method for increasing the speed of an erase operation during a multiple sector fast erase mode.
One type of memory device that has found wide commercial success in the electronic industry is commonly referred to as flash memory. This commercial success is due in part to the ability of flash memory devices to store electronic data over long periods of time without an electric power supply. In addition, flash memory devices are erasable and programmable on-board by the end users of the electronic devices which include the flash memory. This combined functionality is especially useful in electronic device applications like cellular telephones, personal digital assistants, and computer BIOS storage, and other applications where power supply is intermittent and programmability is desired.
Flash memory devices are made up of an array of individual memory transistors, or cells, which are similar to those used in other types of memory devices. Flash memory devices, however, typically achieve their non-volatility functionality by the addition of a floating gate between the control gate and the substrate region of the memory transistors. Like other memory devices, the transistors are oriented into rows and columns to form the array of transistors. As is common in the memory device art, common wordlines are electrically connected to the control gates of the cells within each row of the array. Similarly, common bitlines are electrically connected to the drain regions of the cells within each column of the array. Finally, a common source line is electrically connected to the source regions of all the cells in the array. In some flash memory devices the array of transistors is subdivided into sectors of separate transistor arrays to provide added flexibility to the programming and erasing operations.
The data stored in each particular cell represents a binary 1 or 0, as is well-known in the art. To perform a program, read, or erase operation on a particular cell in the array, various predetermined voltages are applied to combinations of the wordline, bitline, and source line. By applying the voltages to a particular bitline column, a particular wordline row, and the array source, individual cells at the intersection of the bitline and wordline can be selected to be read or programmed.
To program a cell, the control gate and the drain region of the cell are raised to predetermined programming voltages and the source is grounded. The voltages on the control gate and the drain region cause the generation of hot electrons which are injected onto the floating gate where they become trapped, forming a negative charge on the floating gate. This electron transfer mechanism is often referred to as Channel Hot Electron (CHE) injection. When the programming voltages are removed, the negative charge on the floating gate is maintained, thereby raising the threshold voltage. The threshold voltage is used during reading operations to determine if the cell is in a charged state, or programmed (0), or whether the cell is in an uncharged state, or un-programmed (0).
Cells are read by applying a predetermined voltage to the control gate and the drain region and grounding the source of the cell. The current in the bitline is then sensed. If the cell is programmed, the threshold voltage will be relatively high and the bitline current will be zero or at least relatively low, thus registering a binary 0. On the other hand if the cell is erased, the threshold voltage will be relatively low and the bitline current will be relatively high, thus registering a binary 1.
In contrast to the programming procedure, flash memory devices are typically bulk-erased by simultaneously erasing all the cells in a memory sector. One procedure for erasing an entire memory sector involves applying predetermined voltages to the common source line and wordlines of the sector, while the drain of the cells are left to float. This causes electron tunneling from the floating gate to the source through Fowler-Nordheim (F-N) tunneling, which removes the negative charge from the floating gate of each of the cells in the memory sector.
Cells in the NOR memory configuration are typically erased by applying an erase voltage pulse for a predetermined time frame. Ideally, each cell in the memory sector will require the same amount of time to remove the electrons from the floating gate. In reality, however, erase times among the cells within the memory sector vary, and some of the cells which are subjected to the erase pulse may become over-erased. In an over-erased cell the threshold voltage becomes lowered to a point where the cell causes electrical current to leak to the bitline even if the gate of the cell is grounded. Excessive current leakage can prevent proper reading and programming of other cells.
To correct excessive current leakage, the bitlines are typically verified during an Automatic Program Disturb Erase Verify (xe2x80x9cAPDEVxe2x80x9d) operation that occurs automatically as part of an Automatic Program Disturb Erase (xe2x80x9cAPDExe2x80x9d) operation, which is part of an erase operation. The APDEV operation verifies that each bitline does not contribute excessive current leakage above a predetermined allowable leakage, or reference current, and takes corrective action if necessary. During the APDEV operation, a bias voltage is applied to all the wordlines in the sector, and each bitline in the sector is sequentially sensed for current above the reference current. If the bitline current is above the reference current, an APDE operation is performed on all the cells in the bitline. The APDE operation is a soft program that mainly affects the over-erased cells by raising their threshold voltage. After the APDE operation, the bitline current is sensed again and the APDE operation is repeated if necessary until the current sensed in the bitline during the APDEV operation is below the reference current.
One method which can be used to increase the speed of the erasing operations involves selecting several sectors at one time and performing the bulk erase procedure on all these sectors simultaneously. This method of erasing is sometimes referred to as a fast erase mode. The particular combination of multiple sectors that are selected for simultaneous erasing in this mode is usually chosen by the memory device""s state machine, or logic center, and depends primarily on the erase current. For example, in many cases a full erasure of all the sectors is not possible because the total erase current required would surpass the amount of current available to the memory chip.
Some of the erasing procedures, however, become inefficient when performed on several sectors simultaneously. One such procedure is the APDEV and the APDE. As previously explained, the APDEV operation verifies that current leakage is below a reference current. However, when multiple sectors are selected during the APDEV operation, the current leakage that is measured is multiplied by the number of sectors selected since the bitlines from each of these sectors are verified simultaneously. This situation can significantly increase the time required for the APDEV and the APDE procedure to be completed because the allowable current leakage in each of the bitlines is effectively lowered in the multiple sector erase. The ability of APDE to correct the current leakage is exponentially reduced as the threshold voltage of the over-erased cells is increased, which means the total time required for the APDEV and APDE functions will grow exponentially.
In one example of this problem, the reference current is 5 xcexcA. Thus, when a single sector is selected, the APDEV function measures and verifies that the current leakage in each bitline in the sector is less than 5 xcexcA. The APDEV function takes about 400 ns per sixteen bitlines, to complete. Each time a bitline is found that has a current leakage greater than 5 xcexcA, the APDE function applies a voltage pulse to the bitline to correct the current leakage. The APDE function takes about 100 xcexcs to complete each time it is required. In tests, the total time to complete the APDEV and APDE functions on a single sector has been estimated to be 527.6 xcexcs. In contrast to this single sector APDEV, when four sectors are simultaneously selected, the APDEV function will measure the current leakage from one bitline in each of the four sectors simultaneously. As a result, the current leakage in each of four different bitlines will be added together. Thus, the reference current of 5 xcexcA will be more difficult to satisfy, requiring more APDE pulses to correct the current leakage. In tests, the total time to complete the APDEV and APDE functions on four sectors simultaneously has been estimated to be 10.56 ms.
In order to minimize the time required for the APDEV and the APDE functions, latches store the status of the address lines that define the sector column positions. When the APDEV function is entered, the multiple sector group is no longer selected, and each of the individual sectors in the multiple sector group are selected in separate sequence steps provided by the state machine. The APDEV function, therefore, is performed on each of the sectors in the multiple sector group serially instead of on all of the sectors simultaneously. After the APDEV and the APDE functions are completed, the address lines for the sector column positions are reset to their original status before the APDEV function was performed by the latches.